I have trouble with LA4032. My Chinese friend already sent you description of trouble but has no any answer. Let's I describe here.
This analyzer has no any RLL encoding. When trigger is happens, it starts to collect data as oscilloscope. Of course, buffer will be full little bit more than after 1 seconds. In all cases!
But this behaviour is nice for oscilloscopes with analog data but not for logic analyzers with digital data! All good logic analyzers, such as very expensive BusDoctor or very cheap LA5034 from ZhiYuan (i bougth this analyzer in 2007 in BeiJing, but it has very small buffer) using RLL encode. If digital data is not changes, they are not store data. When data changed, they store either data or timestamp. That is why if data chnages not fast, buffer will be not full during long time.
Of course, your engeniers will not change firmware for change logic. But I can program Spartan-6 FPGA, which is used inside. Also I have high experience of making firmware for FX2LP (Cypress chipset, which is used for USB bridg). But I don't know wiring diagram. At least, I need know pinut of connection channels, RAM and FX2LP.
I understand that you will be afraid to send wiring diagram because I can start to make clones of your device. But FPGA firmware has file *.UCF which is not enough for make clone, but contains all necessary information about pinout. Can you send me this file for make own firmware, which will contain RLL encode for larger collect time? Now LA5034 is powerful toy. Only after add RLL it will be real tool. For now, I lost money. And cannot improve it without pinout or UCF file.
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