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Edited by gf1 at 2019-2-15 05:52
Dear Support,
when both channels are enabled, I notice a time offset/difference between CH1 and CH2, in the amount of about 50ns at >= 10us/div and about 5ns at faster time base settings. This is obviously 1/2 of the ADC clock period, which is used at the particular time base setting.
This is nasty, and it makes particulary X-Y mode quite unreliable (-> what I measure does not reflect the truth)
Example:
The same 1MHz sine wave signal is fed into both, CH1 and CH2, and displayed in X-Y mode. One would expect to see a diagonal line, however, an ellipse is displayed, although there is no phase shift between the signals fed into CH1 and CH2 - it is the same signal (-> same kind of PP-80 probes used for both channels, I also tried alternatively with two 50 Ohm terminated coax cables of the same length - no differece).
The same in the time domain (captured at 10us/div, then frozen and zoom-in):
Do you see any possibility to fix this problem in the FPGA and/or firmware?
Versions of my device:
SOFT 2018120601
PCB 0000000001
FPGA V02
Thanks,
gf1
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